There is a continuing trend in the semiconductor industry to fabricate integrated circuits of increasing complexity. As the complexity of an integrated circuit increases, the costs associated with fabricating the integrated circuit also increase. In order to provide integrated circuit devices having increased functional capability while maintaining control over the costs associated with fabrication, more devices must be included on each semiconductor wafer.
In recent years, integrated circuit fabrication technology has achieved the ability to define circuit components having feature sizes in the sub-micron size range. For example, new photolithographic techniques have been developed using X-ray and pulsed-laser energy sources. Additionally, film deposition technology now exists which can form thin-films having a precisely determined metallurgical composition and thickness. Furthermore, thin-film etching techniques have been developed which are capable of selectively etching one metallurgical composition, while not substantially etching other metallurgical compositions present on the semiconductor substrate.
However, even with the marked advances in fabrication technology, achievement of the necessary packing density and cost control in the manufacture of modern integrated circuits requires further development of circuit designs. Integrated circuit designs which take advantage of the improved capability of present manufacturing technology can substantially reduce the amount of substrate area necessary to fabricate an individual integrated circuit. One important design technique for fabricating devices having a small surface area is to stack metal-oxide-semiconductor (MOS) transistors in a vertical arrangement. Typically, a first transistor is formed in the substrate, having source, drain, and channel regions in the substrate, and a gate electrode overlying the substrate surface. Then, a second transistor is formed in thin-film layers overlying the first transistor. By adding an additional electrical component to the device, the thin-film transistor increases the functional capacity of the device while not consuming additional surface area. Thin-film transistors are especially useful in CMOS logic devices. For example, a CMOS inverter can be fabricated from an N-channel transistor in the substrate and a P-channel load transistor in a thin-film layer overlying the N-channel transistor. CMOS inverters find application in a wide variety of integrated circuit devices. For example, cross-coupled CMOS inverters form the memory storage element of an SRAM memory device.
Although thin-film transistors represent a useful design improvement for the formation of complex integrated circuits, their incorporation into integrated circuits presently requires that additional surface area be provided for the various components of the thin-film transistor. Further, thin-film transistors increase the topographic contrast of an integrated circuit device. Because thin-film transistors require additional layers, which must be formed over existing structures on the substrate surface, the total vertical height of the device is increased. The steep topography of the device can result in the formation of voids in metal leads subsequently formed to connect the device with external circuit elements. Accordingly, new designs which take full advantage of available fabrication technology are necessary to meet the need for high density semiconductor devices.